Field of the Invention
This disclosure relates to sampling circuits and more particularly to reducing metastability exposure associated with sampling circuits.
Description of the Related Art
Sampling circuits can be used to sample values of asynchronous signals. It is desirable that at the clock edge of the clock supplied to the sampling circuit, a sampling circuit evaluates sampled data based on the state of the data setup prior to the clock edge. The circuit of FIG. 1 shows a sampling circuit that samples on the rising edge of the clock signal C. The circuit of FIG. 1 has a long clock to Q (clk-Q) resolution time if the data transitions at an inopportune time relative to the clock. That can cause a metastability exposure. Metastability refers to a circuit, such as a flip-flop, whose output is unstable and oscillates between 0 and 1, eventually settling to either the 0 state or the 1 state. In the circuit shown in FIG. 1, during the evaluation phase, having the data change after the sampling (rising) edge of the clock and before the falling edge of the clock can lead to a false reading. Thus, using the sampling circuit of FIG. 1 in asynchronous sampling applications such as a time-to-digital converter (TDC) can result in false readings. Increasing the size of the feedback devices 101 and 103 used in the sampling circuit to mitigate the likelihood of false readings can slow the internal nodes and reduce speed. In sampling circuits metastability exposure is undesirable and improvements in sampling circuits for asynchronous applications is desirable.